1. Field of the Invention
The present invention relates to technology for early detection of the stable generation of a high-speed clock signal by a high-speed oscillator.
2. Description of the Related Art
Currently, information processing systems that switch between a high-speed clock signal and a low-speed clock signal while operating in order to reduce power consumption are widely used. Specifically, such information processing systems have two operation modes, namely, a normal mode and a standby mode. Normal mode is a mode in which in the information processing system operates with use of a high-speed clock signal supplied by a high-speed oscillator. Standby mode is a mode in which the information processing system stops the oscillation of the high-speed oscillator, and operates with use of a low-speed clock signal supplied by a low-speed oscillator.
When switching from standby mode to normal mode, this kind of information processing system must first detect that the oscillation of the high-speed oscillator is stable, that is to say, that the amplitude and frequency of the high-speed clock signal generated by the high-speed oscillator are stable, before completing the switch to normal mode. This is because if the information processing system operates with use of the high-speed clock signal while the oscillation of the high-speed oscillator is not stable, there will be problems such as the information processing system running out of control since an unstable high-speed clock signal is being supplied.
In view of this, there is conventional technology for detecting that the oscillation of the high-speed oscillator is stable by preliminarily estimating the number of high-speed clock signals that are generated before the oscillation becomes stable, and presuming that the oscillation has stabilized once the high-speed oscillator has generated a sufficient number of high-speed clock signals. For example, the high-speed clock signals generated by the high-speed oscillator are successively input to a counter. After the counter has counted a predetermined number of high-speed clock signal inputs, the information processing system completes the switch to normal mode.
However, due to manufacturing variations etc., high-speed oscillators differ between each other in how high-speed clock signals are generated before the oscillation stabilizes. Examples of such differences include the period of time before oscillation stabilizes, and how the frequency of the high-speed clock signal increases before oscillation stabilizes. Also, external factors such as heat can delay the stabilization of the oscillation of the high-speed oscillator.
In view of this, patent document 1 discloses technology for counting only high-speed clock signals whose amplitudes are stable, instead of counting all of the high-speed clock signals that have been generated. Specifically the technology of patent document 1 includes a semiconductor that only passes signals whose amplitude is greater than or equal to a predetermined threshold value, and makes use of the semiconductor to count the number of signals whose amplitude surpasses the threshold value, that is to say, the number of high-speed clock signals whose amplitude is stable.
Patent document 1: Japanese Patent Application Publication No. H03-95606
However, the technology of patent document 1 lacks reliability in the precision of the detection. This is because the technology of patent document 1 cannot actually detect that the frequency of a high-speed clock signal has stabilized. In other words, the fact that a predetermined number of high-speed clock signals has been counted does not necessarily mean that the frequency of the high-speed clock signal has stabilized when the predetermined number is reached. Therefore, there is the risk that the technology of patent document 1 will falsely detect that the oscillation of the high-speed oscillator is stable, even though the frequency of the high-speed clock signal has not actually stabilized.
Also, when a high-speed oscillator begins oscillating, the frequencies of the generated high-speed clock signals rise above and fall below the predetermined frequency of a stable high-speed clock signal, as they gradually converge to the predetermined frequency. Therefore, the fact that the frequency of a generated high-speed clock signal has reached a predetermined frequency does not necessarily mean that the oscillation of the high-speed oscillator has stabilized.
The technology of patent document 1 does not detect that the frequency of the high-speed clock is stable until the predetermined number of clock pulses is counted by the counter, even if the oscillation of the high-speed oscillator has already stabilized. Therefore, even if the frequency of the high-speed clock signal has stabilized, the information processing system cannot switch to normal mode until the predetermined number of clock pulses is counted, thereby causing unnecessary power consumption and delaying the beginning of operation with use of the high-speed clock signal. Particularly in cases in which an information processing system frequently switches between standby mode and normal mode during operation, such as the case of a wireless communication device that performs intermittent reception, there is a desire to minimize the negative effect on battery lifetime that unnecessary power consumption has, the production of heat that accompanies unnecessary power consumption, the delay in processing commencement, etc.